#define iosapic_disable_level_irq mask_irq
#define iosapic_ack_level_irq nop
-struct hw_interrupt_type irq_type_iosapic_level = {
+static hw_irq_controller irq_type_iosapic_level = {
.typename = "IO-SAPIC-level",
.startup = iosapic_startup_level_irq,
.shutdown = iosapic_shutdown_level_irq,
#define iosapic_disable_edge_irq nop
#define iosapic_end_edge_irq nop
-struct hw_interrupt_type irq_type_iosapic_edge = {
+static hw_irq_controller irq_type_iosapic_edge = {
.typename = "IO-SAPIC-edge",
.startup = iosapic_startup_edge_irq,
.shutdown = iosapic_disable_edge_irq,
unsigned long polarity, unsigned long trigger)
{
irq_desc_t *idesc;
- struct hw_interrupt_type *irq_type;
+ hw_irq_controller *irq_type;
int rte_index;
int index;
unsigned long gsi_base;
#ifdef CONFIG_SMP
extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
-static struct irqaction ipi_irqaction = {
+static struct irqaction __read_mostly ipi_irqaction = {
.handler = handle_IPI,
#ifndef XEN
.flags = SA_INTERRUPT,
__setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
-static struct irqaction cmci_irqaction = {
+static struct irqaction __read_mostly cmci_irqaction = {
.handler = ia64_mca_cmc_int_handler,
#ifndef XEN
.flags = SA_INTERRUPT,
.name = "cmc_hndlr"
};
-static struct irqaction cmcp_irqaction = {
+static struct irqaction __read_mostly cmcp_irqaction = {
.handler = ia64_mca_cmc_int_caller,
#ifndef XEN
.flags = SA_INTERRUPT,
.name = "cmc_poll"
};
-static struct irqaction mca_rdzv_irqaction = {
+static struct irqaction __read_mostly mca_rdzv_irqaction = {
.handler = ia64_mca_rendez_int_handler,
#ifndef XEN
.flags = SA_INTERRUPT,
.name = "mca_rdzv"
};
-static struct irqaction mca_wkup_irqaction = {
+static struct irqaction __read_mostly mca_wkup_irqaction = {
.handler = ia64_mca_wakeup_int_handler,
#ifndef XEN
.flags = SA_INTERRUPT,
};
#ifdef CONFIG_ACPI
-static struct irqaction mca_cpe_irqaction = {
+static struct irqaction __read_mostly mca_cpe_irqaction = {
.handler = ia64_mca_cpe_int_handler,
#ifndef XEN
.flags = SA_INTERRUPT,
.name = "cpe_hndlr"
};
-static struct irqaction mca_cpep_irqaction = {
+static struct irqaction __read_mostly mca_cpep_irqaction = {
.handler = ia64_mca_cpe_int_caller,
#ifndef XEN
.flags = SA_INTERRUPT,
#endif
}
-static struct irqaction perfmon_irqaction = {
+static struct irqaction __read_mostly perfmon_irqaction = {
.handler = pfm_interrupt_handler,
#ifndef XEN
.flags = SA_INTERRUPT,
}
#endif
-struct hw_interrupt_type irq_type_sn = {
+static hw_irq_controller irq_type_sn = {
#ifndef XEN
.name = "SN hub",
#else
/* nuthing to do... */
}
-struct hw_interrupt_type irq_type_ia64_lsapic = {
+hw_irq_controller irq_type_ia64_lsapic = {
.typename = "LSAPIC",
.startup = lsapic_noop_startup,
.shutdown = lsapic_noop,
#define shutdown_none disable_none
#define end_none enable_none
-struct hw_interrupt_type no_irq_type = {
+hw_irq_controller no_irq_type = {
"none",
startup_none,
shutdown_none,
raise_softirq(TIMER_SOFTIRQ);
}
-static struct irqaction xen_timer_irqaction = {
+static struct irqaction __read_mostly xen_timer_irqaction = {
.handler = (void *) xen_timer_interrupt,
.name = "timer"
};
/*
* IRQ Chip for MSI HPET Devices,
*/
-static struct hw_interrupt_type hpet_msi_type = {
+static hw_irq_controller hpet_msi_type = {
.typename = "HPET-MSI",
.startup = hpet_msi_startup,
.shutdown = hpet_msi_shutdown,
/* Adjust the GSI assert counts for the ISA IRQ line state.
* This relies on the PCI IRQ state being loaded first. */
- for ( irq = 0; irq < 16; irq++ )
+ for ( irq = 0; platform_legacy_irq(irq); irq++ )
if ( test_bit(irq, &hvm_irq->isa_irq.i) )
hvm_irq->gsi_assert_count[hvm_isa_irq_to_gsi(irq)]++;
enable_8259A_irq(irq);
}
-static struct hw_interrupt_type i8259A_irq_type = {
+static struct hw_interrupt_type __read_mostly i8259A_irq_type = {
.typename = "XT-PIC",
.startup = startup_8259A_irq,
.shutdown = disable_8259A_irq,
spin_unlock_irqrestore(&i8259A_lock, flags);
}
-static struct irqaction cascade = { no_action, "cascade", NULL};
+static struct irqaction __read_mostly cascade = { no_action, "cascade", NULL};
void __init init_IRQ(void)
{
set_intr_gate(vector, interrupt[vector]);
}
- for (irq = 0; irq < 16; irq++) {
+ for (irq = 0; platform_legacy_irq(irq); irq++) {
struct irq_desc *desc = irq_to_desc(irq);
struct irq_cfg *cfg = desc->chip_data;
/*
* # of IRQ routing registers
*/
-int nr_ioapic_registers[MAX_IO_APICS];
+int __read_mostly nr_ioapic_registers[MAX_IO_APICS];
+int __read_mostly nr_ioapics;
int disable_timer_pin_1 __initdata;
*/
static int EISA_ELCR(unsigned int irq)
{
- if (irq < 16) {
+ if (platform_legacy_irq(irq)) {
unsigned int port = 0x4d0 + (irq >> 3);
return (inb(port) >> (irq & 7)) & 1;
}
return 0;
}
-static struct hw_interrupt_type ioapic_level_type;
-static struct hw_interrupt_type ioapic_edge_type;
+static hw_irq_controller ioapic_level_type;
+static hw_irq_controller ioapic_edge_type;
#define IOAPIC_AUTO -1
#define IOAPIC_EDGE 0
entry.vector = vector;
ioapic_register_intr(irq, IOAPIC_AUTO);
- if (!apic && (irq < 16))
+ if (!apic && platform_legacy_irq(irq))
disable_8259A_irq(irq);
}
cfg = irq_cfg(irq);
unsigned long flags;
spin_lock_irqsave(&ioapic_lock, flags);
- if (irq < 16) {
+ if (platform_legacy_irq(irq)) {
disable_8259A_irq(irq);
if (i8259A_irq_pending(irq))
was_pending = 1;
return 0; /* don't check for pending */
}
-int ioapic_ack_new = 1;
+int __read_mostly ioapic_ack_new = 1;
static void setup_ioapic_ack(char *s)
{
if ( !strcmp(s, "old") )
* edge-triggered handler, without risking IRQ storms and other ugly
* races.
*/
-static struct hw_interrupt_type ioapic_edge_type = {
+static hw_irq_controller ioapic_edge_type = {
.typename = "IO-APIC-edge",
.startup = startup_edge_ioapic_irq,
.shutdown = disable_edge_ioapic_irq,
.set_affinity = set_ioapic_affinity_irq,
};
-static struct hw_interrupt_type ioapic_level_type = {
+static hw_irq_controller ioapic_level_type = {
.typename = "IO-APIC-level",
.startup = startup_level_ioapic_irq,
.shutdown = mask_IO_APIC_irq,
* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
* which implement the MSI or MSI-X Capability Structure.
*/
-struct hw_interrupt_type pci_msi_type = {
+hw_irq_controller pci_msi_type = {
.typename = "PCI-MSI",
.startup = startup_msi_irq,
.shutdown = shutdown_msi_irq,
{
int irq;
/* Xen: This is way simpler than the Linux implementation. */
- for (irq = 0; irq < 16 ; irq++)
+ for (irq = 0; platform_legacy_irq(irq); irq++)
if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
make_8259A_irq(irq);
}
static void end_lapic_irq(unsigned int irq) { /* nothing */ }
-static struct hw_interrupt_type lapic_irq_type = {
+static hw_irq_controller lapic_irq_type = {
.typename = "local-APIC-edge",
.startup = NULL, /* startup_irq() not used for IRQ0 */
.shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
/*
* IRQs < 16 are already in the irq_2_pin[] map
*/
- if (irq >= 16)
+ if (!platform_legacy_irq(irq))
add_pin_to_irq(irq, ioapic, pin);
vector = assign_irq_vector(irq);
ioapic_register_intr(irq, edge_level);
- if (!ioapic && (irq < 16))
+ if (!ioapic && platform_legacy_irq(irq))
disable_8259A_irq(irq);
spin_lock_irqsave(&ioapic_lock, flags);
#include <public/physdev.h>
/* opt_noirqbalance: If true, software IRQ balancing/affinity is disabled. */
-int opt_noirqbalance = 0;
+int __read_mostly opt_noirqbalance = 0;
boolean_param("noirqbalance", opt_noirqbalance);
unsigned int __read_mostly nr_irqs_gsi = 16;
struct irq_cfg __read_mostly *irq_cfg = NULL;
-static struct timer *irq_guest_eoi_timer;
+static struct timer *__read_mostly irq_guest_eoi_timer;
static DEFINE_SPINLOCK(vector_lock);
static struct timer irq_ratelimit_timer;
/* irq_ratelimit: the max irq rate allowed in every 10ms, set 0 to disable */
-unsigned int __read_mostly irq_ratelimit_threshold = 10000;
+static unsigned int __read_mostly irq_ratelimit_threshold = 10000;
integer_param("irq_ratelimit", irq_ratelimit_threshold);
/* Must be called when irq disabled */
#define shutdown_none disable_none
#define end_none enable_none
-struct hw_interrupt_type no_irq_type = {
+hw_irq_controller no_irq_type = {
"none",
startup_none,
shutdown_none,
/* MP IRQ source entries */
int mp_irq_entries;
-int nr_ioapics;
-
int pic_mode;
unsigned long mp_lapic_addr;
}
}
- for (i = 0; i < 16; i++) {
+ for (i = 0; platform_legacy_irq(i); i++) {
switch (mpc_default_type) {
case 2:
if (i == 0 || i == 13)
* Use the default configuration for the IRQs 0-15. Unless
* overriden by (MADT) interrupt source override entries.
*/
- for (i = 0; i < 16; i++) {
+ for (i = 0; platform_legacy_irq(i); i++) {
int idx;
for (idx = 0; idx < mp_irq_entries; idx++) {
}
}
-static struct irqaction irq0 = { timer_interrupt, "timer", NULL };
+static struct irqaction __read_mostly irq0 = { timer_interrupt, "timer", NULL };
/* ------ Calibrate the TSC -------
* Return processor ticks per second / CALIBRATE_FRAC.
return alloc_vcpu(d, vcpu_id, cpu_id);
}
-static unsigned int extra_dom0_irqs = 256, extra_domU_irqs = 32;
+static unsigned int __read_mostly extra_dom0_irqs = 256;
+static unsigned int __read_mostly extra_domU_irqs = 32;
static void __init parse_extra_guest_irqs(const char *s)
{
if ( isdigit(*s) )
}
-static struct hw_interrupt_type iommu_msi_type = {
+static hw_irq_controller iommu_msi_type = {
.typename = "AMD_IOV_MSI",
.startup = iommu_msi_startup,
.shutdown = iommu_msi_mask,
spin_unlock_irqrestore(&iommu->register_lock, flags);
}
-static struct hw_interrupt_type dma_msi_type = {
+static hw_irq_controller dma_msi_type = {
.typename = "DMA_MSI",
.startup = dma_msi_startup,
.shutdown = dma_msi_mask,
extern __u8 isa_irq_to_vector_map[16];
#define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)]
-extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
+extern hw_irq_controller irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
extern int assign_irq_vector (int irq); /* allocate a free vector */
extern void free_irq_vector (int vector);
#endif
static inline void
-hw_resend_irq (struct hw_interrupt_type *h, unsigned int vector)
+hw_resend_irq (hw_irq_controller *h, unsigned int vector)
{
platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
}
#include <irq_vectors.h>
#include <asm/percpu.h>
-#define IO_APIC_IRQ(irq) (((irq) >= 16 && (irq) < nr_irqs_gsi) \
- || (((irq) < 16) && (1<<(irq)) & io_apic_irqs))
+#define IO_APIC_IRQ(irq) (platform_legacy_irq(irq) ? \
+ (1 << (irq)) & io_apic_irqs : \
+ (irq) < nr_irqs_gsi)
#define IO_APIC_VECTOR(irq) (irq_vector[irq])
#define MSI_IRQ(irq) ((irq) >= nr_irqs_gsi && (irq) < nr_irqs)
#define LEGACY_VECTOR(irq) ((irq) + FIRST_LEGACY_VECTOR)
#define LEGACY_IRQ_FROM_VECTOR(vec) ((vec) - FIRST_LEGACY_VECTOR)
-#define vector_to_irq(vec) (vector_irq[vec])
-#define irq_to_desc(irq) &irq_desc[(irq)]
+#define irq_to_desc(irq) (&irq_desc[irq])
+#define irq_cfg(irq) (&irq_cfg[irq])
#define MAX_GSI_IRQS PAGE_SIZE * 8
#define MAX_NR_IRQS (2 * MAX_GSI_IRQS)
-#define irq_cfg(irq) &irq_cfg[(irq)]
-
struct irq_cfg {
int vector;
cpumask_t domain;
*/
#define NR_HP_RESERVED_VECTORS 20
-extern struct hw_interrupt_type pci_msi_type;
+extern const struct hw_interrupt_type pci_msi_type;
/*
* MSI-X Address Register
void (*set_affinity)(unsigned int irq, cpumask_t mask);
};
-typedef struct hw_interrupt_type hw_irq_controller;
+typedef const struct hw_interrupt_type hw_irq_controller;
#include <asm/irq.h>